1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device; in particular to a NAND flash memory using an internal power supply voltage lower than an external power supply voltage. More particularly, the present invention relates to a nonvolatile semiconductor memory device, which is built in a low-power consumption mobile phone, in particular.
2. Description of the Related Art
A nonvolatile semiconductor memory device, for example, a NAND flash memory has a need to meet the requirements of a mass capacity with a scale reduction of a design rule. For this reason, a block size, a page size or the number of planes increases. In particular, the page size or the number of planes increase, and thereby, the number of sense amplifiers for detecting data of a bit line increases. In order to keep the layout pattern of a sense amplifier to a predetermined bit line pitch, there is a need to make the layout area of a sense amplifier circuit as small as possible. For this reason, there is a tendency for the gate width of a transistor used for the sense amplifier circuit to be reduced.
Usually, if the gate width of transistor is reduced, a phenomenon such that a threshold voltage becomes high (narrow channel effect) occurs. However, the following problem arises in the case of employing an insulating film for an isolation insulating film between transistors, a gate insulating film or intergate insulating film of a memory cell transistor peculiar to a flash memory or a charge storage layer of the memory cell transistor. Namely, the process of forming the foregoing insulating film is carried out, and thereby, leak current flows through a channel edge of a transistor. As a result, the threshold voltage of transistor is reduced; therefore, the cutoff current (Ioff) of nMOS and pMOS transistors increases. The standby current of a memory is the total sum of the cutoff current of transistor and a current of a circuit through which a steady-state current flows. For this reason, when the cutoff current increases, a current (standby current) of a memory in a standby state increases.
According to a normal physical model, if the gate width of a MOS transistor is reduced, the threshold voltage of transistor increases by narrow channel effect while the cutoff current decreases.
However, there is the following case depending on a material for processing an isolation insulating film between transistors, that is, shallow trench isolation (STI). Namely, if the gate width of transistor is reduced, the threshold voltage of transistor is reduced while the cutoff current increases. The following example is given as one of the foregoing physical model. Specifically, if positive fixed charges (+) are generated in an isolation region depending on the material of the isolation region, negative charges (−) are induced along the channel length direction of an nMOS transistor. As a result, even if the nMOS transistor is in a cutoff state, a region where much leak current flows through channel both edges occurs. The gate width of transistor becomes narrow, and thereby, a ratio occupied by the foregoing region where much leak current flows through channel both edges becomes high; for this reason, the cutoff current increases. Therefore, it is not expected to reduce the cutoff current by a reduction of the gate width of transistor. In fact, a degree that the cutoff current increases becomes high, and the leak current increases beyond narrow channel effect; as a result, the reduction of the gate width is a factor of causing a tendency for the cutoff current to increase.
As described above, in the NAND flash memory, the number of bit-line sense amplifier circuits increases with a scale reduction of a design rule. Further, if the gate width of transistor used for a sense amplifier is reduced, and thereby, the cutoff current increases, there is the possibility that a standby current increases. As a result, there is the possibility that the lifetime of a battery becomes short in mobile electronic apparatuses such as a mobile phone and a mobile music player having a built-in NAND flash memory.
In particular, in a NAND flash memory of a 70 nm-after process generation design rule, the cutoff current of an nMOS transistor in the standby current largely depends on the nMOS transistor in a sense amplifier. For this reason, it is important to reduce the cutoff current of the nMOS transistor in the sense amplifier.
Jpn. Pat. Appln. KOKAI Publication No. 2002-373942 discloses the following SRAM. The SRAM includes an operation power step-down circuit and a standby power step-down circuit, which generate operation internal power and standby internal power, respectively. Further, each output node is connected to an internal power source line. In this case, the foregoing two power step-down circuits each include a reference voltage generation circuit, which generates a reference voltage different from each other. The operation power step-down circuit outputs a first internal power supply voltage lower than an external power supply voltage in a normal operation using a first reference voltage generated by a first reference voltage generation circuit. Further, the circuit is controlled so that it is in an output off state in a standby time. The standby power step-down circuit always outputs a second internal power supply voltage lower than the first internal power supply voltage to an internal power source line using a second reference voltage generated by a second reference voltage generation circuit.